_mm256_testnzc_pd, _mm_testnzc_pd

Performs a packed bit test of two 256-bit float64 or 128-bit float64 vectors to set ZF and CF flags. The corresponding Intel® AVX instruction is VTESTPD.

Syntax

extern __m256d __cdecl _mm256_testnzc_pd(__m256d s1, __m256d s2);

extern __m128d __cdecl _mm_testnzc_pd(__m128d s1, __m256d s2);

Arguments

s1

first source float64 vector

s2

second source float32 vector

Description

Allows setting of both the ZF and CF flags. The ZF flag is set based on the result of a bitwise AND operation between the first and second source vectors. The CF flag is set based on the result of a bitwise AND and logical NOT operation between the first and second source vectors. The corresponding instruction, VTESTPD, sets the ZF and CF flags if all the resulting bits are 0. If the resulting bits are non-zeros, the instruction clears the ZF and CF flags.

The _mm_testnzc_pd intrinsic sets the ZF and CF flags according to results of the 128-bit float64 source vectors. The _m256_testnzc_pd intrinsic sets the ZF and CF flags according to the results of the 256-bit float64 source vectors.

Note iconNote

Intel® AVX instructions include a full compliment of 128-bit SIMD instructions. Such Intel® AVX instructions, with vector length of 128-bits, zeroes the upper 128 bits of the YMM register. The lower 128 bits of the YMM register is aliased to the corresponding SIMD XMM register.

Returns

Non-zero if CF flag is set

Zero if the CF flag is not set