The prototypes for Intel® Streaming SIMD Extensions 2 (Intel® SSE2) intrinsics for cacheability support are in the emmintrin.h header file.
void _mm_stream_pd(double *p, __m128d a)
Stores the data in a to the address p without polluting caches. The address p must be 16-byte aligned. If the cache line containing address p is already in the cache, the cache will be updated. p[0] := a0 p[1] := a1
void _mm_stream_si128(__m128i *p, __m128i a)
Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated. Address p must be 16-byte aligned.
void _mm_stream_si32(int *p, int a)
Stores the 32-bit integer data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated.
void _mm_stream_si64(__int64 *p, __int64 a)
Stores the 64-bit integer data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache is updated.
void _mm_clflush(void const*p)
Cache line containing p is flushed and invalidated from all caches in the coherency domain.