The prototypes for Streaming SIMD Extensions (SSE) intrinsics for cacheability support are in the xmmintrin.h header file.
Intrinsic Name |
Operation |
Corresponding |
---|---|---|
_mm_prefetch |
Load |
PREFETCH |
_mm_stream_pi |
Store |
MOVNTQ |
_mm_stream_ps |
Store |
MOVNTPS |
_mm_sfence |
Store fence |
SFENCE |
void _mm_prefetch(char const*a, int sel)
Loads one cache line of data from address a to a location "closer" to the processor. The value sel specifies the type of prefetch operation: the constants _MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, and _MM_HINT_NTA should be used for IA-32, corresponding to the type of prefetch instruction. The constants _MM_HINT_T1, _MM_HINT_NT1, _MM_HINT_NT2, and _MM_HINT_NTA should be used for systems based on IA-64 architecture.
void _mm_stream_pi(__m64 *p, __m64 a)
Stores the data in a to the address p without polluting the caches. This intrinsic requires you to empty the multimedia state for the MMX register. See the topic The EMMS Instruction: Why You Need It.
void _mm_stream_ps(float *p, __m128 a)
Stores the data in a to the address p without polluting the caches. The address must be 16-byte-aligned.
void _mm_sfence(void)
Guarantees that every preceding store is globally visible before any subsequent store.