Cacheability Support Operations for Streaming SIMD Extensions 2

The prototypes for Streaming SIMD Extensions 2 (SSE2) intrinsics for cacheability support are in the emmintrin.h header file.

Intrinsic Name

Operation

Corresponding
SSE2 Instruction

_mm_stream_pd

Store

MOVNTPD

_mm_stream_si128

Store

MOVNTDQ

_mm_stream_si32

Store

MOVNTI

_mm_stream_si64 Store

MOVNTI

_mm_clflush

Flush

CLFLUSH

_mm_lfence

Guarantee visibility

LFENCE

_mm_mfence

Guarantee visibility

MFENCE

 

void _mm_stream_pd(double *p, __m128d a)

Stores the data in a to the address p without polluting caches. The address p must be 16-byte aligned. If the cache line containing address p is already in the cache, the cache will be updated. p[0] := a0 p[1] := a1

p[0]

p[1]

a0

a1

 

void _mm_stream_si128(__m128i *p, __m128i a)

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated. Address p must be 16-byte aligned.

*p

a

 

void _mm_stream_si32(int *p, int a)

Stores the 32-bit integer data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated.

*p

a

 

void _mm_stream_si64(__int64 *p, __int64 a)

Stores the 64-bit integer data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache is updated.

*p

a

 

void _mm_clflush(void const*p)

Cache line containing p is flushed and invalidated from all caches in the coherency domain.

*p

a

 

void _mm_lfence(void)

Guarantees that every load instruction that precedes, in program order, the load fence instruction is globally visible before any load instruction which follows the fence in program order.

 

void _mm_mfence(void)

Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction which follows the fence in program order.