Performs a packed bit test of two 256-bit or 128-bit float32 vectors to set ZF and CF flags. The corresponding Intel® AVX instruction is VTESTPS.
extern __m256 __cdecl _mm256_testnzc_ps(__m256 s1, __m256 s2); |
extern __m128 __cdecl _mm_testnzc_ps(__m128 s1, __m128 s2); |
s1 |
first source float32 vector |
s2 |
second source float32 vector |
Allows setting of both the ZF and CF flags. The ZF flag is set based on the result of a bitwise AND operation between the first and second source vectors. The CF flag is set based on the result of a bitwise AND and logical NOT operation between the first and second source vectors. The corresponding instruction, VTESTPS, sets the ZF and CF flags if all the resulting bits are 0. If the resulting bits are non-zeros, the instruction clears the ZF and CF flags.
The _mm_testnzc_ps intrinsic sets the ZF and CF flags according to results of the 128-bit float64 source vectors. The _m256_testnzc_ps intrinsic sets the ZF and CF flags according to the results of the 256-bit float64 source vectors.
Intel® AVX instructions include a full compliment of 128-bit SIMD instructions. Such Intel® AVX instructions, with vector length of 128-bits, zeroes the upper 128 bits of the YMM register. The lower 128 bits of the YMM register is aliased to the corresponding SIMD XMM register.
Non-zero if CF flag is set
Zero if the CF flag is not set